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designed for pulse-width-modulated (pwm) control of dc motors, the A5950 is capable of peak output currents up to 3 a and operating voltages up to 40 v . input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied pwm control signals. internal synchronous rectification control circuitry is provided to lower power dissipation during pwm operation. internal circuit protection includes overcurrent protection, motor lead short to ground or supply, thermal shutdown with hysteresis, undervoltage monitoring of vbb, and crossover- current protection. the A5950 is supplied in a low-profile 4 mm 4 mm 16-contact qfn (suffix eu) package with wettable flank option (suffix -p), or a 16-lead etssop (suffix lp), all three with exposed power tab for enhanced thermal performance. A5950-ds, rev. 2 mco-0000177 ? overcurrent protection (ocp) ? motor lead short-to-ground protection ? motor lead short-to-battery protection ? motor short protection ? low-power standby mode ? fault output ? adjustable current limit option ? current-to-voltage output ? synchronous rectification C high-side ? internal uvlo ? crossover -current protection ? thermal warning and shutdown function ? aec-q100 grade 1 qualified C k version dc motor driver packages: figure 1: functional block diagram not to scale A5950 features and benefits description may 11, 2017 16-lead qfn with exposed themal pad and wettable flank (suffix eu, option -p) 16-lead tssop with exposed themal pad (suffix lp) control logic out2 vbb phase enable charge pump load supply disable vref 7 v gnd out1 lss vcp cp1 cp2 ocl1 resetn faultn r sense (optional) 500 mv aiout 5 mode uvlo twarn ocp ocl2 oclsel 10 ocl2 16-lead qfn with exposed themal pad (suffix eu, option -t)
2 absolute maximum ratings characteristic symbol notes rating unit load supply voltage v bb 40 v motor outputs v out C2 to 42 v lss v lss 0.5 v t w < 200 ns 2.5 v output current i out continuous [1] 3 a transient output current i outpk t w < 500 ns internally limited a vref v ref C0.3 to 6 v logic input voltage range v in C0.3 to 6 v junction temperature t j 150 c storage temperature range t stg C55 to 150 c operating temperature range t a range g C40 to 105 c range k C40 to 125 c [1] power dissipation and thermal limits must be observed. selection guide part number operating ambient temperature range t a (c) packaging packing A5950geusr-t C40 to 105 16-lead qfn with exposed pad 6000 pieces per 13-in. reel A5950glptr-t C40 to 105 16-lead tssop with exposed pad 4000 pieces per 13-in. reel A5950keusr-j C40 to 125 16-lead qfn with exposed pad and wettable flank 6000 pieces per 13-in. reel A5950klptr-t C40 to 125 16-lead tssop with exposed pad 4000 pieces per 13-in. reel thermal characteristics : may require derating at maximum conditions; see application information characteristic symbol test conditions [2] value unit package thermal resistance r qja 16-lead tssop (suffix lp) jedec hi-k board 34 c/w 2 layer pcb, 1-in. 2 copper 51 c/w 16-lead qfn (suffix eu) jedec hi-k board 36 c/w 2 layer pcb, 1-in. 2 copper tbd c/w [2] additional thermal information available on the allegro website. specifications dc motor driver A5950 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
3 terminal list table name number function eu lp aiout 8 14 analog sense voltage output cp1 11 1 charge pump capacitor cp2 10 16 charge pump capacitor enable 6 12 logic control input faultn 1 7 open drain logic output, active low gnd 12 2 ground terminal lss 14 4 sense voltage mode 7 13 logic control input oclsel 4 10 logic control input outa 13 3 motor output outb 16 6 motor output phase 5 11 logic control input resetn 2 8 logic control input, active low vbb 15 5 supply voltage vcp 9 15 charge pump capacitor vref 3 9 analog input to set current limit C pad pad exposed pad of the package providing enhanced thermal dissipation 16-lead qfn (eu) package pinout diagram pinout diagrams and terminal list table pad 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 outb vbb lss outa phase enable mode aiout gnd cp1 cp2 vcp faultn resetn vref oclsel cp1 gnd outa lss vbb outb faultn resetn cp2 vcp aiout mode enable phase oclsel vref 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 pad 16-lead tssop (lp) package pinout diagram dc motor driver A5950 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
4 characteristics symbol test conditions min. typ. max. unit general vbb supply current i bb outputs off or brake mode C 5.8 9 ma i bb(standby) standby mode C 1 5 a output drivers source driver on resistance r dson(source) i = 3 a, t j = 25c, v bb = 8 v C 335 C m? i = 3 a, t j = 125c, v bb = 8 v C 530 700 m? i = 3 a, t j = 25c, v bb = 5.5 v C 370 C m? i = 3 a, t j = 125c, v bb = 5.5 v C 590 775 m? sink driver on resistance r dson(sink) i = 3 a, t j = 25c, v bb = 8 v C 365 C m? i = 3 a, t j = 125c, v bb = 8 v C 590 775 m? i = 3 a, t j = 25c, v bb = 5.5 v C 390 C m? i = 3 a, t j = 125c, v bb = 5.5 v C 670 875 m? body diode forward voltage v f i = 3 a C 1.15 1.4 v output rise time t r v bb = 12 v, 10% to 90% 50 100 200 ns output fall time t f v bb = 12 v, 90% to 10% 50 100 200 ns dead t ime (crossover) t d C 350 550 ns logic input and output logic output voltage v o i = 2 ma, fault asserted C 0.2 0.5 v logic output leakage i fltn v = 5 v C C 5 a logic input v oltage v ih phase, enable, mode, oclsel 2.0 C 5.5 v v il phase, enable, mode, oclsel 0 C 0.8 v v ihresetn resetn 2.5 C 5.5 v v ilresetn resetn 0 C 0.4 v logic input hysteresis v hys phase, enable, mode, oclsel 200 355 500 mv logic input pull-up current i pu oclsel, mode; v in = 0 v C20 C55 C90 a logic input pull-down resistor r pd resetn, phase, enable 25 50 80 k? electrical characteristics: g range version: valid at t a = 25c, v bb = 5.5 to 40 v (unless noted otherwise) k range v ersion: valid at t a = C40c to 125c, v bb = 5.5 to 40 v (unless noted otherwise) [1] for input and output current specifcations, negative current is defned as coming out of (sourcing) the specifed device pin. [2] for range g devices, specifed limits are tested at a single temperature and assured over operating temperature range by design and characterization. dc motor driver A5950 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
5 characteristics symbol test conditions min. typ. max. unit pwm timing blank time t blk 2.7 3.2 3.7 s fixed off-time t off 22 25.5 29 s percent fast decay p fd internal pwm chop 16 18 20 % vref input current i vref C5 <1 5 a vref input range v ref 0 C 4.5 v current sense accuracy, external a vrev v ref = 2 v, v ref / v lss 9.5 10 10.5 v / v v ref = 250 mv, v ref / v lss 8.4 10 11.6 v / v sense trip level, internal v trip oclsel = low 450 500 550 mv aiout gain a v i = 200 a, v lss = 50 to 200 mv 4.3 5 5.7 v / v i = 200 a, v lss = C50 to C200 mv C4.3 C5 C5.7 v / v power up delay t pu C 250 400 s protection circuits overcurrent threshold i ocp 3.0 C C a overcurrent blank time t ocblk 2.9 3.4 3.9 s overcurrent off-time t ocp 1.0 1.2 1.4 ms uvlo enable threshold v bbuvlo v bb rising 5.1 C 5.4 v uvlo hysteresis v bbuvlo 250 300 350 mv vcp undervoltage v cpuvlo v cp falling 4.0 4.5 5.0 v thermal warning temperature t jw temperature increasing C 160 C c thermal warning hysteresis t jwhys recovery = t jw C t j C 20 C c thermal shutdown temperature t jsd temperature increasing 155 175 C c thermal shutdown hysteresis t jsdhys recovery = t jsd C t j C 20 C c electrical characteristics (continued): g range version: valid at t a = 25c, v bb = 5.5 to 40 v (unless noted otherwise) k range v ersion: valid at t a = C40c to 125c, v bb = 5.5 to 40 v (unless noted otherwise) [1] for input and output current specifcations, negative current is defned as coming out of (sourcing) the specifed device pin. [2] for range g devices, specifed limits are tested at a single temperature and assured over operating temperature range by design and characterization. dc motor driver A5950 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
6 functional description device operation the A5950 is designed to operate dc motors. the output drivers are capable of 40 v and 3 a peak operating currents. actual 100% steady-state dc current capability depends on thermal capability of the package and pcb, and ambient temperature. n-channel dmos drivers feature internal synchronous rectification to reduce power dissipation. peak current can be regulated by fixed off-time pulse- width-modulated (pwm) control circuitry. protection circuitry includes thermal shutdown, protection against shorted loads, or protection against output shorts to ground or supply. undervoltage lockout prevents damage by keeping the outputs off until the driver has enough power supply voltage to operate normally. internal pwm current control when the oclsel input is left open or tied high, peak output current is set by sensing the current through an external sense resistor. i peak = v ref / (10 r sense ) when the peak current is exceeded, the driver will operate in mixed decay mode for fixed time t off before re-enabling the next drive cycle. to disable the current control feature, leave oclsel open or tie oclsel high, and connect lss to gnd. blank function the internal current sense circuit is ignored for some time after pwm transitions so as not to falsely sense overcurrent events due to motor capacitance and switching transients. this blank time, typically 3 s, results in a minimum on-time of the pwm. standby mode low-power standby mode is activated when resetn is low. low- power standby mode disables most of the internal circuitry, including the charge pump and the regulator. when the A5950 is coming out of standby mode, the charge pump should be allowed to reach its regulated voltage (a maximum delay of 400 s) before any pwm commands are issued to the device. overcurrent protection a current monitor will protect the ic from damage due to output shorts. if a short is detected, the ic will disable the outputs. the fault latch is cleared after a timer of duration t ocp expires, and the outputs are re-enabled. during ocp events, the absolute maximum ratings may be exceeded for a short time before the device latches off. thermal monitoring if the die temperature increases to approximately t jsd , the full bridge outputs will be disabled unit the internal temperature falls below a hysteresis level of t jsdhys . thermal warning occurs approximately 20 degrees less than t jsd . thermal warning triggers a fault but does not disable the drivers. ocl option if the oclsel input is left open or tied high, inrush and stall current can be controlled by selection of vref and the sense resistor value. if the oclsel input is connected to gnd, the vref pin is ignored, and the bridge outputs are latched off when the voltage on sense exceeds 500 mv typically. while the outputs are latched off in this condition, the faultn output will be asserted and pulled low. as with ocp events, the device will then be re-enabled after a timer of duration tocp expires. faultn output faultn is an open-drain output and is driven low to indicate any of the following conditions: 1. ocp fault event C short to vbb, gnd, shorted load 2. ocl event (if oclsel = low) 3. thermal warning 4. undervoltage (vbb or vcp) aiout an analog output can be used to monitor the load current flowing through the external sense resistor (if a sense resistor is installed). positive voltage on the sense resistor is gained by 5 and output on the aiout terminal. negative voltage on the sense resistor is gained by C5 and output on the aiout terminal. as the load current does not flow through the sense resistor during a slow-decay (brake) condition, the aiout output is approximately 0 v when in slow-decay. dc motor driver A5950 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
7 table 1: control logic resetn phase enable mode i > i cl out1 out2 function 1 1 1 x false h l forward 1 0 1 x false l h reverse 1 x 0 1 false h h brake (slow decay) 1 1 0 0 false l h fast decay sr [1] 1 0 0 0 false h l fast decay sr [1] 1 1 1 x true l/h h chop (mixed decay) [1] 1 0 1 x true h l/h chop (mixed decay) [1] 0 x x x x z z standby mode [1] outputs change to hi-z state when in fast decay and load current approaches zero. dc motor driver A5950 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
8 package outline drawings 0.95 c seating plane c 0.08 17x 16 16 2 1 1 2 16 2 1 a a terminal #1 mark area coplanarity includes exposed thermal pad and terminals b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only (reference jedec mo-220wggc) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c d d c reference land pattern layout (reference ipc7351 qfn65p400x400x80-17w2m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 4.10 0.35 0.65 4.10 0.65 0.75 0.05 0.30 0.05 0.40 0.10 2.70 2.70 4.00 0.15 4.00 0.15 2.70 2.70 b pcb layout reference view figure 2: eu package, 16-lead qfn with exposed thermal pad dc motor driver A5950 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
9 figure 3: eu package, 16-lead qfn with exposed thermal pad and wettable flank c seating plane c 0.08 17x 16 16 2 1 1 2 a a terminal #1 mark area coplanarity includes exposed thermal pad and terminals b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only (reference jedec mo-220) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c c 0.65 bsc 0.75 0.05 0.30 0.05 0.55 0.10 2.15 0.10 2.15 0.10 4.00 0.10 4.00 0.10 detail a detail a terminal length 0.55 0.10 terminal thickness 0.203 ref 0.05 ref 0.10 ref slp plated area 0.20 0.10 0.25 0.375 ref b dc motor driver A5950 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
10 figure 4: lp package, 16-lead tssop with exposed thermal pad a 1.20 (max) 0.100 0.025 0.30 0.19 0.20 0.09 8o 0o 0.60 0.15 1.00 (ref) c seating plane c 0.10 16x 0.65 (bsc) 0.25 21 16 5.00 0.10 4.40 0.10 6.40 0.20 gauge plane seating plane a b b c exposed thermal pad (bottom surface); dimensions may vary with device 1 d branded face 2.997 2.997 for reference only ? not for tooling use (reference mo-153 abt) dimensions in millimeters. no tt o scale dimensions exclusive of mold ash, gate burrs, and dambar protrusions exact case and lead conguration at supplier discretion within limits shown terminal #1 mark area branding scale and appearance at supplier discretion standard branding reference vi ew yyww nnnnnnn llll = device part number = supplier emblem = last two digits of year of manufacture = week of manufacture = characters 5-8 of lot number n y w l dc motor driver A5950 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
11 for the latest version of this document, visit our website: www.allegromicro.com revision history number date description C november 14, 2016 initial release 1 april 24, 2017 updated selection guide 2 may 11, 2017 corrected packing options in selection guide copyright ?2017, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegros product can reasonably be expected to cause bodily harm. the information included herein is believed to be accurate and reliable. however, allegro microsystems, llc assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. dc motor driver A5950 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com

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